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| kl05p48m48sf1 kl05 sub-family data sheet supports: mkl05z8vfk4, mkl05z16vfk4, mkl05z32vfk4, mkl05z8vlc4, mkl05z16vlc4, mkl05z32vlc4, mkl05z8vfm4, mkl05z16vfm4, mkl05z32vfm4, mkl05z16vlf4, MKL05Z32VLF4 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 105c ? performance C up to 48 mhz arm? cortex-m0+ core ? memories and memory interfaces C up to 32 kb program flash memory C up to 4 kb ram ? clocks C 32 khz to 40 khz or 3 mhz to 32 mhz crystal oscillator C multi-purpose clock source ? system peripherals C nine low-power modes to provide power optimization based on application requirements C 4-channel dma controller, supporting up to 63 request sources C cop software watchdog C low-leakage wakeup unit C swd interface and micro trace buffer C bit manipulation engine (bme) ? security and integrity modules C 80-bit unique identification (id) number per chip ? human-machine interface C low-power hardware touch sensor interface (tsi) C general-purpose input/output ? analog modules C 12-bit sar adc C 12-bit dac C analog comparator (cmp) containing a 6-bit dac and programmable reference input ? timers C two 2-channel timer/pwm (tpm) C periodic interrupt timers C 16-bit low-power timer (lptmr) C real-time clock ? communication interfaces C one 8-bit spi module C i2c module C one low power uart module freescale semiconductor document number: kl05p48m48sf1 data sheet: technical data rev. 3, 11/29/2012 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2012 freescale semiconductor, inc.
table of contents 1 ordering parts ........................................................................... 3 1.1 determining valid orderable parts...................................... 3 2 part identification ...................................................................... 3 2.1 description......................................................................... 3 2.2 format ............................................................................... 3 2.3 fields ................................................................................. 3 2.4 example ............................................................................ 4 3 terminology and guidelines ...................................................... 4 3.1 definition: operating requirement...................................... 4 3.2 definition: operating behavior ........................................... 4 3.3 definition: attribute ............................................................ 5 3.4 definition: rating ............................................................... 5 3.5 result of exceeding a rating .............................................. 6 3.6 relationship between ratings and operating requirements...................................................................... 6 3.7 guidelines for ratings and operating requirements............ 7 3.8 definition: typical value..................................................... 7 3.9 typical value conditions ................................................... 8 4 ratings ...................................................................................... 8 4.1 thermal handling ratings ................................................... 8 4.2 moisture handling ratings .................................................. 9 4.3 esd handling ratings ......................................................... 9 4.4 voltage and current operating ratings ............................... 9 5 general ..................................................................................... 9 5.1 ac electrical characteristics .............................................. 9 5.2 nonswitching electrical specifications ............................... 10 5.2.1 voltage and current operating requirements ......... 10 5.2.2 lvd and por operating requirements ................. 11 5.2.3 voltage and current operating behaviors .............. 12 5.2.4 power mode transition operating behaviors .......... 12 5.2.5 power consumption operating behaviors .............. 13 5.2.6 designing with radiated emissions in mind ........... 20 5.2.7 capacitance attributes .......................................... 20 5.3 switching specifications..................................................... 21 5.3.1 device clock specifications ................................... 21 5.3.2 general switching specifications .......................... 21 5.4 thermal specifications ....................................................... 22 5.4.1 thermal operating requirements ........................... 22 5.4.2 thermal attributes ................................................. 22 6 peripheral operating requirements and behaviors .................... 23 6.1 core modules .................................................................... 23 6.1.1 swd electricals ................................................... 23 6.2 system modules ................................................................ 24 6.3 clock modules ................................................................... 24 6.3.1 mcg specifications ............................................... 24 6.3.2 oscillator electrical specifications ......................... 25 6.4 memories and memory interfaces ..................................... 28 6.4.1 flash electrical specifications................................ 28 6.5 security and integrity modules .......................................... 29 6.6 analog ............................................................................... 29 6.6.1 adc electrical specifications ................................. 29 6.6.2 cmp and 6-bit dac electrical specifications ......... 33 6.6.3 12-bit dac electrical characteristics ..................... 34 6.7 timers................................................................................ 37 6.8 communication interfaces ................................................. 37 6.8.1 spi switching specifications .................................. 37 6.8.2 i2c......................................................................... 41 6.8.3 uart .................................................................... 41 6.9 human-machine interfaces (hmi)...................................... 42 6.9.1 tsi electrical specifications ................................... 42 7 dimensions ............................................................................... 42 7.1 obtaining package dimensions ......................................... 42 8 pinout ........................................................................................ 42 8.1 kl05 signal multiplexing and pin assignments .................. 42 8.2 kl05 pinouts ..................................................................... 44 9 revision history ........................................................................ 48 kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 2 freescale semiconductor, inc. 1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: pkl05 and mkl05 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q kl## a fff r t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification kl## kinetis family ? kl05 a key attribute ? z = cortex-m0+ fff program flash memory size ? 8 = 8 kb ? 16 = 16 kb ? 32 = 32 kb r silicon revision ? (blank) = main ? a = revision after main table continues on the next page... ordering parts kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 3 field description values t temperature range (c) ? v = C40 to 105 pp package identifier ? fk = 24 qfn (4 mm x 4 mm) ? lc = 32 lqfp (7 mm x 7 mm) ? fm = 32 qfn (5 mm x 5 mm) ? lf = 48 lqfp (7 mm x 7 mm) cc maximum cpu frequency (mhz) ? 4 = 48 mhz n packaging type ? r = tape and reel ? (blank) = trays 2.4 example this is an example part number: mkl05z8vlc4 3 terminology and guidelines 3.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 example this is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v terminology and guidelines kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 4 freescale semiconductor, inc. 3.2 definition: operating behavior an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 example this is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 3.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 3.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. terminology and guidelines kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 5 3.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v 3.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 3.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation terminology and guidelines kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 6 freescale semiconductor, inc. 3.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 3.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: terminology and guidelines kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 7 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 4 ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . ratings kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 8 freescale semiconductor, inc. 4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 4.4 voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 120 ma v dio digital pin input voltage (except reset) C0.3 v dd + 0.3 v v aio analog pins 1 and reset pin input voltage C0.3 v dd + 0.3 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 5 general general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 9 5.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. figure 1. input signal measurement reference all digital i/o switching characteristics, unless otherwise specified, assume: 1. output pins ? have c l =30pf loads, ? are slew rate disabled, and ? are normal drive strength 5.2 nonswitching electrical specifications 5.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v table continues on the next page... general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 10 freescale semiconductor, inc. table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes i icio i/o pin dc injection current single pin ? v in < v ss -0.3v (negative current injection) ? v in > v dd +0.3v (positive current injection) -3 +3 ma 1 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection ? positive current injection -25 +25 ma v ram v dd voltage required to retain ram 1.2 v 1. all analog pins are internally clamped to v ss and v dd through esd protection diodes. if v in is greater than v aio_min (=v ss -0.3v) and v in is less than v aio_max (=v dd +0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if these limits cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v aio_min -v in )/|i ic |. the positive injection current limiting resistor is calcualted as r=(v in -v aio_max )/|i ic |. select the larger of these two calculated resistances. 5.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling v dd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 40 mv table continues on the next page... general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 11 table 2. v dd supply lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising thresholds are falling threshold + hysteresis voltage 5.2.3 voltage and current operating behaviors table 3. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage normal drive pad ? 2.7 v v dd 3.6 v, i oh = -5 ma ? 1.71 v v dd 2.7 v, i oh = -1.5 ma v dd C 0.5 v dd C 0.5 v v 1 v oh output high voltage high drive pad ? 2.7 v v dd 3.6 v, i oh = -18 ma ? 1.71 v v dd 2.7 v, i oh = -6 ma v dd C 0.5 v dd C 0.5 v v 1 i oht output high current total for all ports 100 ma v ol output low voltage normal drive pad ? 2.7 v v dd 3.6 v, i ol = 5 ma ? 1.71 v v dd 2.7 v, i ol = 1.5 ma 0.5 0.5 v v 1 v ol output low voltage high drive pad ? 2.7 v v dd 3.6 v, i ol = 18 ma ? 1.71 v v dd 2.7 v, i ol = 6 ma 0.5 0.5 v v 1 i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range 1 a 2 i in input leakage current (per pin) at 25 c 0.025 a 2 i in input leakage current (total all pins) for full temperature range 41 a 2 i oz hi-z (off-state) leakage current (per pin) 1 a r pu internal pullup resistors 20 50 k 3 1. pta12, pta13, ptb0 and ptb1 i/o have both high drive and normal drive capability selected by the associated ptx_pcrn[dse] control bit. all other gpios are normal drive only. 2. measured at v dd = 3.6 v 3. measured at v dd supply voltage = v dd min and vinput = v ss general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 12 freescale semiconductor, inc. 5.2.4 power mode transition operating behaviors all specifications except t por and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 48 mhz ? bus and flash clock = 24 mhz ? fei clock mode table 4. power mode transition operating behaviors symbol description min. typ. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.8 v to execution of the first instruction across the operating temperature range of the chip. 300 s ? vlls0 run 95 115 s ? vlls1 run 93 115 s ? vlls3 run 42 53 s ? lls run 4 4.6 s ? vlps run 4 4.4 s ? stop run 4 4.4 s 5.2.5 power consumption operating behaviors table 5. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_runco run mode current in compute operation - 48 mhz core / 24 mhz flash / bus clock disabled, code of while(1) loop executing from flash ? at 3.0 v 4.1 5.2 ma 2 i dd_run run mode current - 48 mhz core / 24 mhz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash ? at 3.0 v 4.9 5.6 ma 2 table continues on the next page... general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 13 table 5. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_run run mode current - 48 mhz core / 24 mhz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash ? at 3.0 v ? at 25 c ? at 125 c 5.6 6 6.8 7.2 ma ma 2 , 3 i dd_wait wait mode current - core disabled / 48 mhz system / 24 mhz bus / flash disabled (flash doze enabled), all peripheral clocks disabled ? at 3.0 v 3.0 4.2 ma 2 i dd_wait wait mode current - core disabled / 24 mhz system / 24 mhz bus / flash disabled (flash doze enabled), all peripheral clocks disabled ? at 3.0 v 2.4 3.36 ma 2 i dd_pstop2 stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 mhz bus ? at 3.0 v 2.25 3.38 ma 2 i dd_vlprco very-low-power run mode current in compute operation - 4 mhz core / 0.8 mhz flash / bus clock disabled, code of while(1) loop executing from flash ? at 3.0 v 182 522 a 4 i dd_vlpr very-low-power run mode current - 4 mhz core / 0.8 mhz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash ? at 3.0 v 213.33 577.8 a 4 i dd_vlpr very-low-power run mode current - 4 mhz core / 0.8 mhz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash ? at 3.0 v 242.8 631.8 a 3 , 4 i dd_vlpw very-low-power wait mode current - core disabled / 4 mhz system / 0.8 mhz bus / flash disabled (flash doze enabled), all peripheral clocks disabled ? at 3.0 v 106.1 399.42 a 4 table continues on the next page... general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 14 freescale semiconductor, inc. table 5. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_stop stop mode current ? at 3.0 v ? at 25 c ? at 50 c ? at 70 c ? at 85 c ? at 105 c 273 281.2 301.6 331 406.6 441 620 647.64 710.64 1001.84 a i dd_vlps very-low-power stop mode current ? at 3.0 v ? at 25 c ? at 50 c ? at 70 c ? at 85 c ? at 105 c 3.08 5.46 12.08 22.89 53.24 16.01 34.73 46.73 77.37 190.28 a i dd_lls low-leakage stop mode current ? at 3.0 v ? at 25 c ? at 50 c ? at 70 c ? at 85 c ? at 105 c 1.7 3 5.8 10.4 24 3.69 22 28.19 40.29 65.5 a i dd_vlls3 very-low-leakage stop mode 3 current ? at 3.0 v ? at 25 c ? at 50 c ? at 70 c ? at 85 c ? at 105 c 1.3 2.3 4.4 8 18.6 3 11.04 13.68 20.14 37.82 a i dd_vlls1 very-low-leakage stop mode 1 current ? at 3.0 v ? at 25c ? at 50c ? at 70c ? at 85c ? at 105c 0.78 1.5 3.3 6.3 15.2 1.6 13.61 15.59 16.68 26.40 a table continues on the next page... general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 15 table 5. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vlls0 very-low-leakage stop mode 0 current (smc_stopctrl[porpo] = 0) ? at 3.0 v ? at 25 c ? at 50 c ? at 70 c ? at 85 c ? at 105 c 449.6 1200 2900 5900 14800 959.2 12155.08 15323.29 16384.55 26773.45 na i dd_vlls0 very-low-leakage stop mode 0 current (smc_stopctrl[porpo] = 1) ? at 3.0 v ? at 25 c ? at 50 c ? at 70 c ? at 85 c ? at 105 c 221.7 1000 2600 5600 14400 894.24 3784.55 12018.39 18722.23 24665.06 na 5 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. mcg configured for fei mode. 3. incremental current consumption from peripheral activity is not included. 4. mcg configured for blpi mode. 5. no brownout table 6. low power mode peripheral adders typical value symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 56 a i irefsten32khz 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 52 a i erefsten4mhz external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 228 237 245 251 258 ua table continues on the next page... general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 16 freescale semiconductor, inc. table 6. low power mode peripheral adders typical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. vlls1 vlls3 lls vlps stop 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 na i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a i rtc rtc peripheral adder measured by placing the device in vlls1 mode with external 32 khz crystal enabled by means of the rtc_cr[osce] bit and the rtc alarm set for 1 minute. includes erclk32k (32 khz external crystal) power consumption. 432 357 388 475 532 810 na i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 214 66 237 66 246 66 254 66 260 66 268 a i tpm tpm peripheral adder measured by placing the device in stop or vlps mode with selected clock source configured for output compare generating 100 hz clock signal. no load is placed on the i/o generating the clock signal. includes selected clock source and i/o switching currents. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 86 235 86 256 86 265 86 274 86 280 86 287 a i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 45 a table continues on the next page... general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 17 table 6. low power mode peripheral adders typical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 a 5.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe for run mode, and blpe for vlpr mode ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfa general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 18 freescale semiconductor, inc. 4.00e-03 5.00e-03 6.00e-03 7.00e-03 temperature = 25, v dd = 3, cache = enable, code residence = flash, clocking mode = fbe all peripheral clk gates 000.00e+00 1.00e-03 2.00e-03 3.00e-03 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 1 2 3 4 6 12 24 48 run mode current vs core frequency clk ratio flash-core core freq (mhz) all off all on current consumption on v dd (a) figure 2. run mode supply current vs. core frequency general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 19 200.00e-06 250.00e-06 300.00e-06 350.00e-06 000.00e+00 50.00e-06 100.00e-06 150.00e-06 '1-1 '1-2 '1-2 '1-4 1 2 4 vlpr mode current vs core frequency temperature = 25, v dd = 3, cache = enable, code residence = flash, clocking mode = blpe all peripheral clk gates clk ratio flash-core core freq (mhz) current consumption on v dd (a) all off all on figure 3. vlpr mode current vs. core frequency 5.2.6 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com . 2. perform a keyword search for emc design. 5.2.7 capacitance attributes table 7. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 20 freescale semiconductor, inc. 5.3 switching specifications 5.3.1 device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 48 mhz f bus bus clock 24 mhz f flash flash clock 24 mhz f lptmr lptmr clock 24 mhz vlpr mode 1 f sys system and core clock 4 mhz f bus bus clock 1 mhz f flash flash clock 1 mhz f lptmr lptmr clock 24 mhz f erclk external reference clock 16 mhz f lptmr_pin lptmr clock 24 mhz f lptmr_ercl k lptmr external reference clock 16 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 16 mhz f tpm tpm asynchronous clock 8 mhz f uart0 uart0 asynchronous clock 8 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, and i 2 c signals. symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 external reset and nmi pin interrupt pulse width asynchronous path 100 ns 2 gpio pin interrupt pulse width asynchronous path 16 ns 2 port rise and fall time 36 ns 3 general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 21 1. the greater synchronous and asynchronous timing must be met. 2. this is the shrtest pulse that is guaranteed to be recognized. 3. 75 pf load 5.4 thermal specifications 5.4.1 thermal operating requirements table 8. thermal operating requirements symbol description min. max. unit t j die junction temperature C40 125 c t a ambient temperature C40 105 c 5.4.2 thermal attributes table 9. thermal attributes board type symbol description 48 lqfp 32 lqfp 32 qfn 24 qfn unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 82 88 97 110 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 58 59 34 42 c/w single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 70 74 81 92 c/w four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 52 52 28 36 c/w r jb thermal resistance, junction to board 36 35 13 18 c/w 2 r jc thermal resistance, junction to case 27 26 2.3 3.7 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 8 8 8 10 c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditions natural convection (still air) , or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air) . 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditions junction-to-board . general kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 22 freescale semiconductor, inc. 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditions natural convection (still air) . 6 peripheral operating requirements and behaviors 6.1 core modules 6.1.1 swd electricals table 10. swd full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 swd_clk frequency of operation ? serial wire debug 0 25 mhz j2 swd_clk cycle period 1/j1 ns j3 swd_clk clock pulse width ? serial wire debug 20 ns j4 swd_clk rise and fall times 3 ns j9 swd_dio input data setup time to swd_clk rise 10 ns j10 swd_dio input data hold time after swd_clk rise 0 ns j11 swd_clk high to swd_dio data valid 32 ns j12 swd_clk high to swd_dio high-z 5 ns j2 j3 j3 j4 j4 swd_clk (input) figure 4. serial wire clock input timing peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 23 j11 j12 j11 j9 j10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 5. serial wire data timing 6.2 system modules there are no specifications necessary for the device's system modules. 6.3 clock modules 6.3.1 mcg specifications table 11. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal v dd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature +0.5/-0.7 3 %f dco 1 , 2 table continues on the next page... peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 24 freescale semiconductor, inc. table 11. mcg specifications (continued) symbol description min. typ. max. unit notes f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0 - 70 c 0.4 1.5 %f dco 1 , 2 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal v dd and 25 c 4 mhz f intf_ft frequency deviation of internal reference clock (fast clock) over temperature and voltage factory trimmed at nominal v dd and 25 c +1/-2 3 %f intf_ft 2 f intf_t internal reference frequency (fast clock) user trimmed at nominal v dd and 25 c 3 5 mhz f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs = 00) 640 f fll_ref 20 20.97 25 mhz 3 , 4 mid range (drs = 01) 1280 f fll_ref 40 41.94 48 mhz f dco_t_dmx32 dco output frequency low range (drs = 00) 732 f fll_ref 23.99 mhz 5 , 6 mid range (drs = 01) 1464 f fll_ref 47.97 mhz j cyc_fll fll period jitter ? f vco = 48 mhz 180 ps 7 t fll_acquire fll target frequency acquisition time 1 ms 8 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. the deviation is relative to the factory trimmed frequency at nominal v dd and 25 c, f ints_ft . 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32 = 0. 4. the resulting system clock frequencies must not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature must be considered. 5. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32 = 1. 6. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. this specification is based on standard deviation (rms) of period or frequency. 8. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 oscillator electrical specifications this section provides the electrical characteristics of the module. peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 25 6.3.2.1 oscillator dc electrical specifications table 12. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 500 200 300 950 1.2 1.5 na a a a ma ma 1 i ddosc supply current high gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 400 500 2.5 3 4 a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k table continues on the next page... peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 26 freescale semiconductor, inc. table 12. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using the integrated capacitors when the low frequency oscillator (range = 00) is used. for all other cases external capacitors must be used. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 oscillator frequency specifications table 13. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 48 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fbe to fei mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 27 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. note the 32 khz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 6.4 memories and memory interfaces 6.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 14. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s t hversscr sector erase high-voltage time 13 113 ms 1 1. maximum time based on expectations at cycling end-of-life. 6.4.1.2 flash timing specifications commands table 15. flash command timing specifications symbol description min. typ. max. unit notes t rd1sec1k read 1s section execution time (flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersscr erase flash sector execution time 14 114 ms 2 t rd1all read 1s all blocks execution time 0.5 ms t rdonce read once execution time 25 s 1 t pgmonce program once execution time 65 s t ersall erase all blocks execution time 55 465 ms 2 t vfykey verify backdoor access key execution time 30 s 1 1. assumes 25 mhz flash clock frequency. peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 28 freescale semiconductor, inc. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 6.4.1.3 flash high voltage current behaviors table 16. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 6.4.1.4 reliability specifications table 17. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40c t j 125c. 6.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 6.6 analog 6.6.1 adc electrical specifications all adc channels meet the 12-bit single-ended accuracy specifications. peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 29 6.6.1.1 12-bit adc operating conditions table 18. 12-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd - v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss - v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v 3 v refl adc reference voltage low v ssa v ssa v ssa v 3 v adin input voltage v refl v refh v c adin input capacitance ? 8-/10-/12-bit modes 4 5 pf r adin input resistance 2 5 k r as analog source resistance 12-bit modes f adck < 4 mhz 5 k 4 f adck adc conversion clock frequency 12-bit mode 1.0 18.0 mhz 5 c rate adc conversion rate 12 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 6 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. 3. for packages without dedicated vrefh and vrefl pins, v refh is internally tied to v dda , and v refl is internally tied to v ssa . 4. this resistance is external to mcu. the analog source resistance must be kept as low as possible to achieve the best results. the results in this data sheet were derived from a system which has < 8 analog source resistance. the r as /c as time constant should be kept to < 1ns. 5. to use the maximum adc conversion clock frequency, the adhsc bit must be set and the adlpc bit must be clear. 6. for guidelines and examples of conversion rate calculation, download the adc calculator tool peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 30 freescale semiconductor, inc. r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 6. adc input impedance equivalency diagram 6.6.1.2 12-bit adc electrical characteristics table 19. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 -1.1 to +1.9 -0.3 to 0.5 lsb 4 5 inl integral non- linearity ? 12-bit modes ? <12-bit modes 1.0 0.5 -2.7 to +1.9 -0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12-bit modes ? <12-bit modes -4 -1.4 -5.4 -1.8 lsb 4 v adin = v dda 5 table continues on the next page... peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 31 table 19. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes e q quantization error ? 12-bit modes 0.5 lsb 4 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.715 mv/c v temp25 temp sensor voltage 25 c 719 mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and the adlpc bit (low power). for lowest power operation the adlpc bit must be set, the hsc bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) figure 7. typical enob vs. adc_clk for 12-bit single-ended mode peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 32 freescale semiconductor, inc. 6.6.2 cmp and 6-bit dac electrical specifications table 20. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en = 1, pmode = 1) 200 a i ddls supply current, low-speed mode (en = 1, pmode = 0) 20 a v ain analog input voltage v ss v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en = 1, pmode = 1) 20 50 200 ns t dls propagation delay, low-speed mode (en = 1, pmode = 0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.7 to v dd C 0.7 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 33 40.00e-03 50.00e-03 60.00e-03 70.00e-03 80.00e-03 90.00e-03 cmp hysteresis (v) cmp hysteresis vs vinn 0 1 2 hystctr setting 000.00e+00 10.00e-03 20.00e-03 30.00e-03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cmp hysteresis (v) vinn (v) 3 figure 8. typical hysteresis vs. vin level (v dd = 3.3 v, pmode = 0) 80.00e-03 100.00e-03 120.00e-03 140.00e-03 160.00e-03 180.00e-03 cmp hysteresis (v) cmp hysteresis vs vinn 0 1 2 hystctr setting -20.00e-03 000.00e+00 20.00e-03 40.00e-03 60.00e-03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cmp hysteresis (v) vinn (v) 3 figure 9. typical hysteresis vs. vin level (v dd = 3.3 v, pmode = 1) 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 21. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 3.6 v v dacr reference voltage 1.13 3.6 v 1 t a temperature operating temperature range of the device c c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or the voltage output of the vref module (vref_out) 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 34 freescale semiconductor, inc. 6.6.3.2 12-bit dac operating behaviors table 22. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 250 a i dda_dach p supply current high-speed mode 900 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high-speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance load = 3 k 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 35 figure 10. typical inl error vs. digital code peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 36 freescale semiconductor, inc. figure 11. offset at half scale vs. temperature 6.7 timers see general switching specifications. 6.8 communication interfaces 6.8.1 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. see the spi chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 37 all timing is shown with respect to 20% v dd and 80% v dd thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pf maximum load on all spi pins. table 23. spi master mode timing on slew rate disabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns 6 t su data setup time (inputs) 16 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 10 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph - 25 ns t fi fall time input 11 t ro rise time output 25 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). 2. t periph = 1/f periph table 24. spi master mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns 6 t su data setup time (inputs) 96 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 52 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph - 25 ns t fi fall time input 11 t ro rise time output 36 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). 2. t periph = 1/f periph peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 38 freescale semiconductor, inc. (output) (output) miso (input) mosi (output) ss 1 (output) 2 8 6 7 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 9 5 5 3 (cpol 0) (cpol 1) 4 11 11 10 10 spsck spsck = = 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. figure 12. spi master mode timing (cpha = 0) < table 25. spi slave mode timing on slew rate disabled pads (continued) num. symbol description min. max. unit note 6 t su data setup time (inputs) 2 ns 7 t hi data hold time (inputs) 7 ns 8 t a slave access time t periph ns 3 9 t dis slave miso disable time t periph ns 4 10 t v data valid (after spsck edge) 22 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t periph - 25 ns t fi fall time input 13 t ro rise time output 25 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). 2. t periph = 1/f periph 3. time to data active from high-impedance state 4. hold time to high-impedance state table 26. spi slave mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation 0 f periph /4 hz 1 2 t spsck spsck period 4 x t periph ns 2 3 t lead enable lead time 1 t periph 4 t lag enable lag time 1 t periph 5 t wspsck clock (spsck) high or low time t periph - 30 ns 6 t su data setup time (inputs) 2 ns 7 t hi data hold time (inputs) 7 ns 8 t a slave access time t periph ns 3 9 t dis slave miso disable time t periph ns 4 10 t v data valid (after spsck edge) 122 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t periph - 25 ns t fi fall time input 13 t ro rise time output 36 ns t fo fall time output 1. for spi0 f periph is the bus clock (f bus ). 2. t periph = 1/f periph 3. time to data active from high-impedance state 4. hold time to high-impedance state peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 40 freescale semiconductor, inc. (input) (input) mosi (input) miso (output) ss (input) 2 10 6 7 msb in bit 6 . . . 1 lsb in slave msb slave lsb out bit 6 . . . 1 11 5 5 3 8 (cpol 0) (cpol 1) 4 13 note: not defined 12 12 11 see 13 note 9 see note spsck spsck = = figure 14. spi slave mode timing (cpha = 0) (input) (input) mosi (input) miso (output) 2 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 5 5 10 12 13 11 (cpol 0) (cpol 1) ss (input) 3 12 13 4 note: not defined slave 8 9 see note spsck spsck = = figure 15. spi slave mode timing (cpha = 1) 6.8.2 i 2 c see general switching specifications. 6.8.3 uart see general switching specifications. peripheral operating requirements and behaviors kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 41 6.9 human-machine interfaces (hmi) 6.9.1 tsi electrical specifications table 27. tsi electrical specifications symbol description min. type max unit tsi_runf fixed power consumption in run mode 100 a tsi_runv variable power consumption in run mode (depends on oscillator's current selection) 1.0 128 a tsi_en power consumption in enable mode 100 a tsi_dis power consumption in disable mode 1.2 a tsi_ten tsi analog enable time 66 s tsi_cref tsi reference capacitor 1.0 pf tsi_dvolt voltage variation of vp & vm around nominal values 0.19 1.03 v 7 dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to www.freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 24-pin qfn 98asa00474d 32-pin qfn 98asa00473d 32-pin lqfp 98ash70029a 48-pin lqfp 98ash00962a 8 pinout dimensions kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 42 freescale semiconductor, inc. 8.1 kl05 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 48 lqfp 32 qfn 32 lqfp 24 qfn pin name default alt0 alt1 alt2 alt3 1 1 1 1 ptb6/ irq_2/ lptmr0_alt3 disabled disabled ptb6/ irq_2/ lptmr0_alt3 tpm0_ch3 tpm_clkin1 2 2 2 2 ptb7/ irq_3 disabled disabled ptb7/ irq_3 tpm0_ch2 3 pta14 disabled disabled pta14 tpm_clkin0 4 pta15 disabled disabled pta15 clkout 5 3 3 3 vdd vdd vdd 6 4 4 3 vrefh vrefh vrefh 7 5 5 4 vrefl vrefl vrefl 8 6 6 4 vss vss vss 9 7 7 5 pta3 extal0 extal0 pta3 i2c0_scl i2c0_sda 10 8 8 6 pta4/ llwu_p0 xtal0 xtal0 pta4/ llwu_p0 i2c0_sda i2c0_scl 11 vss vss vss 12 ptb18 disabled disabled ptb18 13 ptb19 disabled disabled ptb19 14 9 9 7 pta5/ llwu_p1/ rtc_clk_in disabled disabled pta5/ llwu_p1/ rtc_clk_in tpm0_ch5 spi0_ss_b 15 10 10 8 pta6/ llwu_p2 disabled disabled pta6/ llwu_p2 tpm0_ch4 spi0_miso 16 11 11 ptb8 adc0_se11 adc0_se11 ptb8 tpm0_ch3 17 12 12 ptb9 adc0_se10 adc0_se10 ptb9 tpm0_ch2 18 pta16/ irq_4 disabled disabled pta16/ irq_4 19 pta17/ irq_5 disabled disabled pta17/ irq_5 20 pta18/ irq_6 disabled disabled pta18/ irq_6 21 13 13 9 ptb10 adc0_se9/ tsi0_in7 adc0_se9/ tsi0_in7 ptb10 tpm0_ch1 22 14 14 10 ptb11 adc0_se8/ tsi0_in6 adc0_se8/ tsi0_in6 ptb11 tpm0_ch0 23 15 15 11 pta7/ irq_7/ llwu_p3 adc0_se7/ tsi0_in5 adc0_se7/ tsi0_in5 pta7/ irq_7/ llwu_p3 spi0_miso spi0_mosi 24 16 16 12 ptb0/ irq_8/ llwu_p4 adc0_se6/ tsi0_in4 adc0_se6/ tsi0_in4 ptb0/ irq_8/ llwu_p4 extrg_in spi0_sck pinout kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 43 48 lqfp 32 qfn 32 lqfp 24 qfn pin name default alt0 alt1 alt2 alt3 25 17 17 13 ptb1/ irq_9 adc0_se5/ tsi0_in3/ dac0_out/ cmp0_in3 adc0_se5/ tsi0_in3/ dac0_out/ cmp0_in3 ptb1/ irq_9 uart0_tx uart0_rx 26 18 18 14 ptb2/ irq_10/ llwu_p5 adc0_se4/ tsi0_in2 adc0_se4/ tsi0_in2 ptb2/ irq_10/ llwu_p5 uart0_rx uart0_tx 27 19 19 15 pta8 adc0_se3/ tsi0_in1 adc0_se3/ tsi0_in1 pta8 28 20 20 16 pta9 adc0_se2/ tsi0_in0 adc0_se2/ tsi0_in0 pta9 29 ptb20 disabled disabled ptb20 30 vss vss vss 31 vdd vdd vdd 32 ptb14/ irq_11 disabled disabled ptb14/ irq_11 extrg_in 33 21 21 pta10/ irq_12 disabled tsi0_in11 pta10/ irq_12 34 22 22 pta11/ irq_13 disabled tsi0_in10 pta11/ irq_13 35 23 23 17 ptb3/ irq_14 disabled disabled ptb3/ irq_14 i2c0_scl uart0_tx 36 24 24 18 ptb4/ irq_15/ llwu_p6 disabled disabled ptb4/ irq_15/ llwu_p6 i2c0_sda uart0_rx 37 25 25 19 ptb5/ irq_16 nmi_b adc0_se1/ cmp0_in1 ptb5/ irq_16 tpm1_ch1 nmi_b 38 26 26 20 pta12/ irq_17/ lptmr0_alt2 adc0_se0/ cmp0_in0 adc0_se0/ cmp0_in0 pta12/ irq_17/ lptmr0_alt2 tpm1_ch0 tpm_clkin0 39 27 27 pta13 tsi0_in9 tsi0_in9 pta13 40 28 28 ptb12 tsi0_in8 tsi0_in8 ptb12 41 pta19 disabled disabled pta19 spi0_ss_b 42 ptb15 disabled disabled ptb15 spi0_mosi spi0_miso 43 ptb16 disabled disabled ptb16 spi0_miso spi0_mosi 44 ptb17 disabled disabled ptb17 tpm_clkin1 spi0_sck 45 29 29 21 ptb13 adc0_se13 adc0_se13 ptb13 tpm1_ch1 rtc_clkout 46 30 30 22 pta0/ irq_0/ llwu_p7 swd_clk adc0_se12/ cmp0_in2 pta0/ irq_0/ llwu_p7 tpm1_ch0 swd_clk 47 31 31 23 pta1/ irq_1/ lptmr0_alt1 reset_b disabled pta1/ irq_1/ lptmr0_alt1 tpm_clkin0 reset_b 48 32 32 24 pta2 swd_dio disabled pta2 cmp0_out swd_dio pinout kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 44 freescale semiconductor, inc. 8.2 kl05 pinouts the following figures show the pinout diagrams for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. ptb18 vss pta4/llwu_p0 pta3 vss vrefl vrefh vdd pta15 pta14 ptb7/irq_3 ptb6/irq_2/lptmr0_alt3 12 11 10 9 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 pta2 pta1/irq_1/lptmr0_alt1 pta0/irq_0/llwu_p7 ptb13 ptb17 ptb16 ptb15 pta19 ptb12 pta13 pta12/irq_17/lptmr0_alt2 ptb5/irq_16 36 35 34 33 ptb4/irq_15/llwu_p6 ptb3/irq_14 pta11/irq_13 pta10/irq_12 32 31 30 29 28 27 26 25 ptb14/irq_11 vdd vss ptb20 pta9 pta8 ptb2/irq_10/llwu_p5 ptb1/irq_9 pta18/irq_6 pta17/irq_5 pta16/irq_4 ptb9 24 23 22 21 20 19 18 17 ptb8 pta6/llwu_p2 pta5/llwu_p1/rtc_clk_in ptb19 16 15 14 13 ptb0/irq_8/llwu_p4 pta7/irq_7/llwu_p3 ptb11 ptb10 figure 16. kl05 48-pin lqfp pinout diagram pinout kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 45 32 31 30 29 28 27 26 25 pta2 pta1/irq_1/lptmr0_alt1 pta0/irq_0/llwu_p7 ptb13 ptb12 pta13 pta12/irq_17/lptmr0_alt2 ptb5/irq_16 ptb9 ptb8 pta6/llwu_p2 pta5/llwu_p1/rtc_clk_in 12 11 10 9 ptb0/irq_8/llwu_p4 pta7/irq_7/llwu_p3 ptb11 ptb10 16 15 14 13 pta9 pta8 ptb2/irq_10/llwu_p5 ptb1/irq_9 24 23 22 21 20 19 18 17 ptb4/irq_15/llwu_p6 ptb3/irq_14 pta11/irq_13 pta10/irq_12 pta4/llwu_p0 pta3 vss vrefl vrefh vdd ptb7/irq_3 ptb6/irq_2/lptmr0_alt3 8 7 6 5 4 3 2 1 figure 17. kl05 32-pin lqfp pinout diagram pinout kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 46 freescale semiconductor, inc. 32 31 30 29 28 27 26 25 pta2 pta1/irq_1/lptmr0_alt1 pta0/irq_0/llwu_p7 ptb13 ptb12 pta13 pta12/irq_17/lptmr0_alt2 ptb5/irq_16 ptb9 ptb8 pta6/llwu_p2 pta5/llwu_p1/rtc_clk_in 12 11 10 9 ptb0/irq_8/llwu_p4 pta7/irq_7/llwu_p3 ptb11 ptb10 16 15 14 13 pta9 pta8 ptb2/irq_10/llwu_p5 ptb1/irq_9 24 23 22 21 20 19 18 17 ptb4/irq_15/llwu_p6 ptb3/irq_14 pta11/irq_13 pta10/irq_12 pta4/llwu_p0 pta3 vss vrefl vrefh vdd ptb7/irq_3 ptb6/irq_2/lptmr0_alt3 8 7 6 5 4 3 2 1 figure 18. kl05 32-pin qfn pinout diagram pinout kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. freescale semiconductor, inc. 47 24 23 22 pta2 pta1/irq_1/lptmr0_alt1 pta0/irq_0/llwu_p7 pta12/irq_17/lptmr0_alt2 ptb5/irq_16 21 20 19 ptb13 pta9 pta8 16 15 ptb4/irq_15/llwu_p6 ptb3/irq_14 18 17 ptb2/irq_10/llwu_p5 ptb1/irq_9 14 13 ptb0/irq_8/llwu_p4 pta7/irq_7/llwu_p3 ptb11 ptb10 12 11 10 9 pta6/llwu_p2 8 pta5/llwu_p1/rtc_clk_in 7 pta4/llwu_p0 pta3 vrefl vss vdd vrefh ptb7/irq_3 ptb6/irq_2/lptmr0_alt3 6 5 4 3 2 1 figure 19. kl05 24-pin qfn pinout diagram 9 revision history the following table provides a revision history for this document. table 28. revision history rev. no. date substantial changes 1 7/2012 initial nda release. 2 9/2012 initial public release. 3 11/2012 completed all the tbds. revision history kl05 sub-family data sheet data sheet, rev. 3, 11/29/2012. 48 freescale semiconductor, inc. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com document number: kl05p48m48sf1 rev. 3, 11/29/2012 information in this document is provided solely to enable system and software implementers to use freescale semiconductors products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "typical" parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals", must be validated for each customer application by customer's technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-complaint and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale's environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. |
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